1. Field of the Invention
The present invention relates to a method of verifying semiconductor integrated circuit reliability, especially, a method of verifying the reliability of interconnect lines in a semiconductor integrated circuit.
2. Description of the Background Art
One of the factors that impair the reliability of metallic interconnect lines in a semiconductor integrated circuit is electromigration. To ensure the reliability of a semiconductor integrated circuit, an electromigration failure rate must be suppressed below a predetermined level, and whether the failure rate is not more than a guaranteed failure rate must be verified at the design stage.
As a conventional way to detect metallic interconnect lines having a high electromigration failure rate in a semiconductor integrated circuit, there is a method using circuit simulations. For example, a circuit simulator called xe2x80x9cSPICE (Simulation Program with Integrated Circuit Emphasis) is used to calculate current waveforms flowing in interconnect lines connected to each node.
Concurrently with this, layout data for the interconnect lines connected to each node is extracted from a circuit layout, and accelerated life evaluation data is obtained using an interconnection test structure. On the basis of the current waveforms from the SPICE simulator, the layout data, and the accelerated evaluation data, the failure rate of each metallic interconnect line due to electromigration is calculated. When the resultant failure rate is more than a reference value, the metallic interconnect line is extracted as having a high failure rate.
This method, however, takes much time to extract layout data for a complex interconnect line and is thus not applicable for a large-scale semiconductor integrated circuit. Further, large-scale circuits require enormous amounts of time for circuit simulations and a mass storage device to store waveform data for each node. This increases the difficulty of applying this method to a large-scale semiconductor integrated circuit.
In addition, input waveforms of circuit simulators such as SPICE cannot cover all circuits, which carries a risk that some non-operating circuits may be left unverified.
A first aspect of the present invention is directed to a method of verifying the reliability of a semiconductor integrated circuit using a cell library database. The semiconductor device includes a plurality of cells connected with each other by at least one intercellular interconnect line. The cell library database contains inner-cell input/output load capacity information including input load capacity and output load capacity of each of the plurality of cells, and information about a way to calculate a failure rate of an inner-cell interconnect line based on load capacity on an external terminal of each of the plurality of cells. The method comprises the steps of: (a) obtaining load capacity on the external terminal on the basis of the inner-cell input/output load capacity information; and (b) calculating a failure rate of an inner-cell interconnect line in a cell which has the external terminal, on the basis of the load capacity on the external terminal according to the way to calculate a failure rate, the steps (a) and (b) being performed for each of the plurality of cells.
According to a second aspect of the present invention, in the method of the first aspect, the step (a) includes the steps of: (a-1) obtaining a sum total of inner-cell input/output load capacities on the external terminal on the basis of the inner-cell input/output load capacity information; (a-2) obtaining wiring capacitance of an intercellular interconnect line which is connected to the external terminal, according to an equation of an intercellular interconnect line with the sum total of inner-cell input/output load capacities as a parameter; and (a-3) obtaining the load capacity on the external terminal by adding the wiring capacitance to the sum total of inner-cell input/output load capacities.
According to a third aspect of the present invention, in the method of the first aspect, the step (a) includes the steps of: (a-1) obtaining a sum total of inner-cell input/output load capacities on the external terminal on the basis of the inner-cell input/output load capacity information; (a-2) obtaining wiring capacitance of an intercellular interconnect line which is connected to the external terminal, on the basis of layout information about the intercellular interconnect line; and (a-3) obtaining the load capacity on the external terminal by adding the wiring capacitance to the sum total of inner-cell input/output load capacities.
According to a fourth aspect of the present invention, in the method of the third aspect, the intercellular interconnect line includes a plurality of intercellular interconnect elements which are connected with each other through via holes and which can be recognized from the layout information about the intercellular interconnect line. The method further comprises the steps of: (c) obtaining a failure rate of each intercellular interconnect element which is longer than a predetermined critical length out of the plurality of intercellular interconnect elements on the basis of the load capacity on the external terminal, and adding up the obtained failure rate of each intercellular interconnect element to obtain a failure rate of the intercellular interconnect line; and (d) obtaining a total failure rate by adding the failure rate of the intercellular interconnect line to the failure rate of the inner-cell interconnect line, the steps (c) and (d) being performed for each of the plurality of cells.
According to a fifth aspect of the present invention, the method of either of the first through third aspects further comprises the steps of: (c) obtaining a failure rate of the intercellular interconnect line on the basis of the load capacity on the external terminal; and (d) obtaining a total failure rate by adding the failure rate of the intercellular interconnect line to the failure rate of the inner-cell interconnect line, the steps (c) and (b) being performed for each of the plurality of cells.
According to a sixth aspect of the present invention, in the method of the fifth aspect, the cell library database further contains directional information indicating whether the external terminal of each of the plurality of cells is a bidirectional terminal that can be both charged and discharged or an unidirectional terminal that can be either charged or discharged, and the step (c) includes the steps of: (c-1) determining whether the external terminal is the bidirectional terminal or the unidirectional terminal on the basis of the directional information; (c-2) when the external terminal is the bidirectional terminal, calculating a failure rate of the intercellular interconnect line according to a first way; and (c-3) when the external terminal is the unidirectional terminal, calculating a failure rate of the intercellular interconnect line according to a second way different from the first way.
According to a seventh aspect of the present invention, the method of either of the first through sixth aspects further comprises the steps of: (e) after the step (a), calculating a mean current value flowing in the intercellular interconnect line on the basis of the load capacity on the external terminal and, when the mean current value is not more than a preset current value, forcefully skipping the calculation of a failure rate of a cell having the external terminal, the step (e) being performed for each of the plurality of cells.
According to an eighth aspect of the present invention, in the method of either of the first through seventh aspects, the cell library database further contains operating-ratio information indicating an operating ratio which is the number of operations of each of the plurality of cells during a predetermined period of time, and the step (b) includes the step of calculating a failure rate of the inner-cell interconnect line in consideration of the operating ratio according to the operating-ratio information.
According to a ninth aspect of the present invention, in the method of either of the fourth through seventh aspects, the cell library database further contains operating-ratio information indicating an operating ratio which is the number of operations of each of the plurality of cells during a predetermined period of time; the step (b) includes the step of calculating a failure rate of the inner-cell interconnect line in consideration of the operating ratio according to the operating-ratio information; and the step (d) includes the step of obtaining a failure rate of the intercellular interconnect line in consideration of the operating ratio according to the operating-ratio information.
According to a tenth aspect of the present invention, the method of either of the fourth through seventh aspects further comprises the step of: (f) when the total failure rate is not less than a reference failure rate, registering information about a cell concerned in a predetermined memory unit or displaying it to a predetermined output device, the step (f) being performed for each of the plurality of cells.
According to an eleventh aspect of the present invention, in the method of either of the first through tenth aspects, the failure rate includes an electromigration failure rate.
A twelfth aspect of the present invention is directed to a cell library database for reliability verification of a semiconductor integrated circuit which includes a plurality of cells connected with each other by at least one intercellular interconnect line. The cell library database contains: inner-cell input/output load capacity information including input load capacity and output load capacity of each of the plurality of cells; and information about a way to calculate a failure rate of an inner-cell interconnect line based on load capacity on an external terminal of each of the plurality of cells.
According to a thirteenth aspect of the present invention, the cell library database of the twelfth aspect further contains: directional information indicating whether the external terminal of each of the plurality of cells is a bidirectional terminal that can be both charged and discharged or a unidirectional terminal that can be either charged or discharged.
According to a fourteenth aspect of the present invention, the cell library database of either of the twelfth and thirteenth aspects further contains: operating-ratio information indicating an operating ratio which is the number of operations of each of the plurality of cells during a predetermined period of time.
In the method of the first aspect, since the steps (a) and (b) are performed according to the inner-cell input/output load capacity information and the way to calculate the failure rate of an inner-cell interconnect line based on the load capacity on the external terminal, both of which are obtained from the cell library database, the failure rate of an inner-cell interconnect line in each of the plurality of cells can be calculated without the use of layout information about the inner-cell interconnect line. This increases processing speed, thereby allowing reliability verification of a large-scale semiconductor integrated circuit. In addition, the execution of the steps (a) and (b) for each of the plurality of cells enables verification without any omission.
In the method of the second aspect, highly accurate load capacity is obtained by adding the wiring capacitance to the sum total of inner-cell input/output load capacities in the step (a-3). This improves the accuracy of the failure rate of an inner-cell interconnect line.
In addition, the use of the equation of an intercellular interconnect line with the sum total of inner-cell input/output load capacities as a parameter in the step (a-2) allows the wiring capacitance of an intercellular interconnect line connected to the external terminal to be obtained at high speed without the use of layout information about the intercellular interconnect line.
In the method of the third aspect, highly accurate load capacity is obtained by adding the wiring capacitance to the sum total of inner-cell input/output load capacities in the step (a-3). This improves the accuracy of the failure rate of an inner-cell interconnect line.
In addition, the use of the layout information about an intercellular interconnect line connected to the external terminal in the step (a-2) allows the wiring capacitance of the intercellular interconnect line to be obtained with high accuracy.
In the method of the fourth aspect, the total failure rate is obtained by adding the failure rate of an intercellular interconnect line to that of an inner-cell interconnect line through the execution of the steps (c) and (d). This improves the accuracy of the total failure rate.
Further, in the step (c), the failure rate of each intercellular interconnect element which is longer than a predetermined critical length is obtained and such failure rates are added up to obtain the failure rate of an intercellular interconnect line. Thus, if the critical length is adjusted so that the failure rate of each intercellular interconnect element which is shorter than the critical length becomes almost zero, it becomes possible to increase the operating speed and to obtain the failure rate of an intercellular interconnect line with high accuracy.
In the method of the fifth aspect, the total failure rate is obtained by adding the failure rate of an intercellular interconnect line to that of an inner-cell interconnect line through the execution of the steps (c) and (d). This allows the total failure rate to be in keeping with the real usage pattern.
In the method of the sixth aspect, the failure rate of an intercellular interconnect line is calculated in different ways depending on whether the external terminal is bidirectional or unidirectional according to the directional information. This improves the accuracy of the failure rate of an intercellular interconnect line.
In the method of the seventh aspect, when the mean current value is not more than a preset current value, the calculation of the failure rate of a cell having the external terminal is forcefully skipped in the step (e). Thus, if the preset current value is adjusted so that the total failure rate becomes almost zero when the mean current value is lower than the preset current value, high speed operation can be achieved without deterioration in the accuracy of verification.
In the method of the eighth aspect, the step (b) includes the step of calculating the failure rate of an inner-cell interconnect line in consideration of the operating ratio according to the operating-ratio information. This improves the accuracy of the failure rate of an inner-cell interconnect line.
In the method of the ninth aspect, the step (b) includes the step of calculating the failure rate of an inner-cell interconnect line in consideration of the operating ratio according to the operating-ratio information. This improves the accuracy of the failure rate of an inner-cell interconnect line.
Further, the step (d) includes the step of obtaining the failure rate of an intercellular interconnect line in consideration of the operating ratio according to the operating-ratio information. This improves the accuracy of the failure rate of an intercellular interconnect line.
In the method of the tenth aspect, when the total failure rate is not less than a reference failure rate, the information about the cell concerned is registered in a predetermined storage unit or displayed to a predetermined output device in the step (f). That is, information about the cell whose failure rate exceeds the reference failure rate can be recorded as a reliability verification result or recognized externally.
In the method of the eleventh aspect, the failure rate includes an electromigration failure rate. Thus, the electromigration failure rate of a large-scale semiconductor integrated circuit can be verified without any omission.
The cell library database of the twelfth aspect contains the inner-cell input/output load capacity information including input load capacity and output load capacity of each of the plurality of cells, and the information about the way to calculate the failure rate of an inner-cell interconnect line based on the load capacity on the external terminal of each of the plurality of cells. The use of this cell library database in the method of the first aspect allows reliability verification of a large-scale semiconductor integrated circuit without any omission.
The cell library database of the thirteenth aspect further contains the directional information indicating whether the external terminal of each of the plurality of cells is a bidirectional terminal that can be both charged and discharged or a unidirectional terminal that can be either charged or discharged. The use of this cell library database in the method of the sixth aspect allows the failure rate of an intercellular interconnect line to be obtained with high accuracy.
The cell library database of the fourteenth aspect further contains the operating-ratio information indicating the number of operations of each of the plurality of cells during a predetermined period of time. The use of this cell library database in the method of the eighth aspect allows the failure rate of an inner-cell interconnect line to be calculated in consideration of the operating ratio with higher accuracy.
Further, the use of this cell library database in the method of the ninth aspect allows the failure rates of an inner-cell interconnect line and an intercellular interconnect line to be calculated in consideration of the operating ratio with higher accuracy.
An object of the present invention is to provide a method of verifying semiconductor integrated circuit reliability, which allows reliability verification of a large-scale semiconductor integrated circuit without any omission.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.